Heterogeneous Integrated Advanced Packaging - Process Integration - Process Capabilities

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Process Integration

Heterogeneous Integrated Advanced Packaging

Optical Communication Device & Chip Fabrication
Novel Nanoelectronic / Optoelectronic Devices
CMOS Processes
Micro-Nano Optical Device Fabrication
MEMS / Microfluidic Chip Fabrication
Heterogeneous Integrated Advanced Packaging

Optical Communication Device & Chip Fabrication
Novel Nanoelectronic / Optoelectronic Devices
CMOS Processes
Micro-Nano Optical Device Fabrication
MEMS / Microfluidic Chip Fabrication
Heterogeneous Integrated Advanced Packaging

Heterogeneous Integration – Advanced Packaging

The platform currently enables submicron to several-hundred-micrometer-scale 3D heterogeneous integration. Through monolithic or hybrid integration approaches, it supports flip-chip bonding, bump interconnects, wafer-level packaging, 2.5D packaging (interposers, RDL), and 3D packaging (TSV, TGV).

Silicon-based multi-chiplet heterogeneous integrated phased-array transceiver front-end

(Figure provided by: Prof. Linsheng Wu’s research group, Shanghai Jiao Tong University)